Audio-gd :: R8,Fully Discrete R-2R Resistor Ladders DAC, Fully Discrete DSD Native decoder, Fully Discrete Real Balance Built in 4 groups DA-7 V2 modules Built In FPGA Processor , Reject The Jitter ,DSD , DXD 32bit / 384K Support From USB / HDMI
Price: 2210.68 EUR ( 1797.30 EUR Net Price)
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DAC R-8 #

Audio-Gd R281

Fully Discrete R-2R Resistor Ladders DAC

Fully Discrete DSD Native decoder

Fully Discrete Real Balance Current Transmission Design

All Digital Settings accessible By Buttons On Front Plate (No need to open the chasis).

4 distinctive types of different algorithms in NOS mode, and 3 types of different oversampling modes,

have 7 different tonal characteristics.

Can be selection by the buttons on front plate.

The R-8 has kept all advantage technology of R-7 but applied SMD technology to lower the cost and price. In sound quality, they are quite close .

Advantages: 1.R-2R will not convert the clock signal into the output signal. 2. R-2R is not sensitive to jitter while Delta-Sigma D/A is much more sensitive to jitter. 3. The output signal is much more precise compared to Delta-Sigma D/A .

Audio-Gd R284

The R-2R DAC is very popular nowadays and available from DIY kits and all the way up to high-end products. In the low range DIY market, the R-2R design is often based on old technology designed a long time ago by MSB and only includes basic R2R ladder design and do not include the wonderful correction design of the original MSB technology. This design uses data shift registers logic chips in series mode to convert the data to an analog signal. The structural R2R technology issues cannot be avoided, and performance is solely depending on the accuracy of the ladder resistors.

In the High-End market, the R2R design is much more complex and reaches performance. A basic R2R ladder is simply not sufficient enough to achieve good performance and sound quality! Some manufacturers are using shift registers design. A less complex and lower performance design based on traditional logic chips working in serial mode to correct the ladder. A far better design switches resistors in parallel mode. An ultra-fast FPGA controls and corrects the R2R ladder. The parallel design mode controls every bit respectively and therefore achieve unprecedented performance. (In parallel mode only 1 clock cycle is needed to output all data; serial design mode needs at minimum 8 up to 24 clock cycles) The parallel design is much more complicated. Once designed properly it can correct every bit of the ladder. Photo below shows a design with such FPGA, can correct the unavoidable imperfections of the R2R ladder caused by tolerance of resistors, glitches to achieve best performance.

Accuracy of the ladder resistors (tolerance): Many people believe the tolerance of the resistors in the ladder is most important to reach best performance. Nowadays 24 bit resolution is standard. What tolerance is needed to achieve 24 bit resolution? When we look at 16 bit the tolerance of 1/66536, 0.1% (1/1000) is far not enough, even a tolerance of 0.01% (1/10000), the best tolerance available in the world today, still cannot handle 16 bit request correctly; we are not even calculating 24 bit here! The tolerance of the resistor will never solve Imperfections of a ladder. This would require resistors with a tolerance of 0.00001% and can handle 24 bit resolution. This is only in theory because the discreteness of the switch logic chips have already too much internal impedance and will destroy the impossible tolerance of a resistor. The solution is to correct the ladder and not only depend on the tolerance of resistors. It’s a combination of both: Ultra-low tolerance resistors controlled by a correction technology using very high speed FPGA are applicable in in our design.